A ferroelectric-gate field effect transistor (FeFET) incorporating a ferroelectric in its gate insulator has come to be attracting attention as a transistor having a memory function. While having long had the problem that its data storage time is short, in patent document 1 an FeFET is shown in which the gate laminate of electrode conductor/ferroelectric/insulator/semiconductor is comprised of metal Pt, SBT (Sr Bi2 Ta2 O9) as a sort of crystal of Bi layered perovskite structure, insulator Hf—Al—O and semiconductor Si, thus of Pt/Sr Bi2 Ta2 O9/Hf—Al—O2/Si. An example of the FeFET is disclosed there in which both the on and off states of a drain current when each measured for a long period of time are continued extremely stably and the ratio of drain currents in the on state and off state after a weak reaches not less than 105. In the same patent document, a good data retention property is disclosed of a FeFET composed of Pt/Sr Bi2 Ta2 O9/Hf O2/Si, too. Thus, it has been demonstrated by patent document 1 that a FeFET acts as a memory transistor in which data is truly retained and stored. In the same patent document, data rewrite withstand property is evaluated and it is disclosed that after rewriting 1012 times, the on time and off states read out are fully discriminated. While a reason for such good data rewrite withstand capability has not yet been clarified, it is deemed to be due to the fact that the ferroelectric is made up of crystal of Bi layer perovskite structure. In the Bi layered perovskite structure, ferroelectricity (i.e. the property that atoms are distorted according to a direction of electric field and after the electric field is removed, the distortion is left and electric polarization is not restored to zero) occurs at portions of the perovskite structure. It appears that a Bi layered oxide substance between the perovskite portions acting as a buffer layer renders a malfunction less liable to occur at an interface with another layer such as of Pt, in data rewriting, to with, during a repetition of the reversal of electric field for writing, thus leading to the good rewrite withstand capability of a FeFET.
In patent document 2, there is disclosed a FeFET using (Bi, Nd)4 Ti3 O12 that is a Bi layer perovskite substance, as the ferroelectric. Non-patent reference 1 discloses the use in FeFETs of (Bi, La)4 Ti3 O12 that is a Bi layer perovskite substance, as the ferroelectric.
Patent document 3 discloses using CSBT (Cax Sr1-x Bi2 Ta2 O9) as the ferroelectric of Bi layer perovskite substance, and that a FeFET composed of Pt/Cax Sr1-xBi2 Ta2 O9/Hf—Al—O/Si processes a good data retention property and a good data rewrite withstand capability.
Upon forming Bi layer perovskite on the insulator/semiconductor, annealing is performed in an oxygen atmosphere for a time period of 10 to 60 minutes to crystallize the Bi layer perovskite, thereby causing it to express the ferroelectricity. It is performed at a temperature preferably from 700 to 830 degrees Celsius, more preferably from 730 to 813 degrees C. Passing the process step of annealing is found to achieve a good data retention and a good rewrite withstand property as mentioned above. By passing the process step of annealing, an interfacial layer is formed at an interface between silicon and the insulator as shown by non-patent reference 2 to 4. Non-patent reference 3 teaches that the interfacial layer is formed mainly composed of SiO2. This connotes that in annealing in an oxygen atmosphere for crystallizing the Bi layer perovskite, a silicon surface is oxidized to form the interfacial layer mainly composed of SiO2. As a result of uniform formation of the interfacial layer, it contributes to development of good electrical characteristics. Non-patent reference 5 discloses an example of development of an NAND flash memory of 64 k bitts with a FeFET as a memory cell by this technique.
There are the following reports of dividing the insulator into two layers. In non-patent reference 6, a film of silicon nitride is formed on silicon and thereafter a film of HfO2 is formed. In non-patent reference 7, a film of oxynitride of silicon is formed on silicon and thereafter HfO2 is formed. In either case, passing the process step of annealing to crystallize the Bi layer perovskite and to develop the ferroelectricity causes an interfacial layer mainly composed of SiO2 to be formed between Si and HfO2. The interfacial layer may contain nitrogen as derived from the film of silicon nitride and/or the film of oxynitride of silicon but is mainly composed of SiO2. The interfacial layer is formed mainly by oxidation of Si, but may be merged with the insulating layer, and may have an insulating material contained therein as an impurity. Note that while non-patent reference 7 shows the range in which the gate voltage is swept is from 1-3.3 volts to 1+3.3 volts, the data given there teaches that the ferroelectric SBT has a thickness as thick as 450 nm and is not suitable for a FeFET to be nanofined.
There is a report regarding the thickness of an interfacial layer which is inspected with a transmission electron microscope as mainly composed of SiO2. Non-patent reference 2 shows that a FeFET composed of Pt/Sr Bi2 Ta2 O9/Hf—Al—O/Si annealed in oxygen at a temperature of 800 degrees C. and for a time period of 60 minutes has an interfacial layer having a thickness of 4.4 nm. Although patent document 2 discloses that SiO2 having a thickness of 2 nm to 5 nm is provided between Hf2 and Si, it is not the thickness of an interfacial layer mainly composed of SiO2, but is the thickness of SiO2 in the insulator prior to annealing for ferroelectric crystallization. There is no mention of the thickness of an interfacial layer mainly composed of SiO2 subsequent to annealing which is effected at a temperature of 700 to 800 degrees C. in an oxygen atmosphere for a time period of 30 minutes for the purposes of annealing for ferroelectric crystallization.
In patent reference 8, it is shown that annealed in oxygen at a temperature of 750 degrees C. for a time period of 30 minutes, a laminate constituted of a film of (Bi, La)4 Ti3 O12 having a thickness of 400 nm on a film of HfO2 having a thickness of 8 nm on Si has an interfacial layer having a thickness of about 5 nm. In non-patent reference 4, it is shown that a FeFET composed of Pt/Cax Sr1-x Bi2 Ta2 O9/Hf—Al—O/Si annealed in oxygen at a temperature of 778 degrees C. for a time period of 30 minutes has an interfacial layer having a thickness of 3.4 nm. In non-patent reference 6, it is shown that a gate laminate composed of Pt/Sr Bi2 Ta2 O9/HfO2/SiN/Si is annealed in oxygen at a temperature of 800 degrees C. for a time period of 1 hour, forming an interfacial layer mainly composed of SiO2 and having a thickness of 4 nm. Thus, annealing in oxygen at a temperature of 750 to 800 degrees C. for a time period of 30 to 60 minutes is shown to form an interfacial layer having a thickness of 3.4 nm to 5 nm. Further lowering the annealing temperature is shown to tend to decrease the thickness of an interfacial layer and to produce a FeFET whose electrical characteristics are not good. A FeFET presenting acceptable characteristics is shown to have an interfacial layer having a thickness of 3.4 nm to 5 nm.
In reducing a FeFET in size, it is required from the technique of microfining such as etching that the height of a gate laminate be reduced. As shown in patent document 1 and non-patent references 6 to 8, the thickness of a ferroelectric is commonly 400 nm or more. While in patent reference 3 Examples are almost of a film of ferroelectric Cax Sr1-x Bi2 Ta2 having a thickness of 200 nm, an Example is shown in which the film thickness is 120 nm. However, the writing voltage is used which in absolute value is as high as 5 volts.
In non-patent reference 9, where a positive voltage for data writing is shown applied to the gate of an FeFET of Pt/Sr Bi2 Ta2 O9/Hf—Al—O/Si, a diagram is discussed of voltage divisions applied to various portions of a gate and energy bands in directions of depth of the gate. Identically computed, there is derived an energy band diagram (FIG. 31) that is equivalent to that of non-patent reference 9. It is assumed that Pt/Sr Bi2 Ta2 O9 (SBT), Hf—Al—O (HAO) and an interfacial layer (II) mainly composed of SiO2 have thicknesses of 200 nm, 7 nm and 3.5 nm, respectively. If it is then assumed that when a writing voltage is applied, an electric polarization of Pmax=2.7 micro C/cm2 is formed in a ferroelectric, an equivalent charge is induced on the gate electrode Pt, and a voltage of 1.20 volts is applied to the ferroelectric, a voltage of 1.06 volts to Hf—Al—O, a voltage of 2.74 volt to the interfacial layer and a surface electrostatic potential of 0.95 volt to Si. A voltage of 5.95 volts as a sum of them is applied the gate metal, Pt. The voltage Vil of 2.74 volts applied to the interfacial layer is derived from dilPmax/(ε0kil O(=2.74 V) where dil is a thickness of the interfacial layer mainly composed of SiO2, and kil is a dielectric constant of the interfacial layer, for which use is made of that of 3.9 of SiO2, and ε0 is the dielectric constant in vacuum. The electric polarization at writing is of a degree of 1 to 3 micro C/cm2. If the polarization is greater than of 3 micro C/cm2, the voltage and electric field applied to the interfacial layer are increased so that there may develop a phenomenon of injection of electrons from the semiconductor side into the gate insulator side. The addition of a phenomenon other than polarization reversal mechanism makes the operation of a FeFET very complicated.
Non-patent reference 10 discloses a FeFET of Al/PTO/Si where PTO is lead titanate in the form of a film whose thickness is 90 nm. Id−Vd characteristics of FeFET is shown which is obtained on sweeping the gate voltage between −4 volts and +4 volts and sweeping it in reciprocation between 1 2 volts and +2 volts. A data retention property with writing voltages of −4 and +4 colts is measured. It is shown that in about 104 seconds, it becomes hard to discriminate an On and an Off states. There is no showing of a data retention property with writing voltages of −2 and +2 volts, nor is a result shown of rewrite withstand test. In non-patent reference 11, a Fe FET of TiN/HfSiO/SiO2/Si is reported where HfSiO is claimed to be a ferroelectric, having a thickness of 8.5 nm. A writing voltage is shown as −3 and 4 volts and, if a manner of expression of the present invention as mentioned hereinafter is followed, its absolute value is 3.5 volts. A data retention property of up to 3×104 seconds is shown but there is no mention of results of rewrite withstand property.